1. Field of the Invention
The present invention relates generally to semiconductor fabrication and, more particularly, to a method for forming a sacrificial polymer upon patterned features to allow those features to be trimmed laterally without incurring much loss vertically.
2. Description of Related Art
The fabrication of an integrated circuit involves numerous processing steps. After impurity regions are formed within a semiconductor substrate and gate conductors are defined upon the substrate, interconnect routing is placed across the substrate and connected to the impurity regions. An interlevel dielectric is formed between the interconnect routing and the substrate to isolate the two levels. Contact openings are formed through the dielectric and filled with a conductive material to electrically link the interconnect routing to select impurity regions in the substrate. Additional levels of interconnect routing separated by interlevel dielectric layers can be formed if desired. Different levels of the interconnect routing can be coupled together with ohmic contacts formed through the dielectric layers. Forming a multi-level integrated circuit in this manner reduces the overall lateral area occupied by the circuit.
Various features of the integrated circuit, e.g., gate conductors, are defined using a technique known as lithography. A photosensitive film, i.e., photoresist, is spin-deposited across a layer of the integrated circuit in which features are to be formed. An optical image is transferred to the photoresist by projecting a form of radiation, typically ultraviolet light, through the transparent portions of a mask plate. A photochemical reaction alters the solubility of the regions of the photoresist exposed to the radiation. The photoresist is washed with a solvent known as a developer to preferentially remove the regions of higher solubility, followed by curing the remaining regions of the photoresist. The portions of the layer below the photoresist which are no longer covered by the photoresist are etched away to define features of the ensuing integrated circuit. The photoresist provides protection for the portions of the layer directly beneath the photoresist from being removed.
Unfortunately, the minimum lateral dimension that can be achieved for a patterned photoresist feature is limited by, among other things, the resolution and the depth-of-focus of the optical system used to project the image onto the photoresist. The term “resolution” describes the ability of an optical system to distinguish closely spaced objects. The term “depth-of-focus” refers to the distance range through which the imaging plane can be moved forward or backward with respect to the optical system while retaining satisfactory sharp focus. In addition, diffraction effects may undesirably occur as the radiation passes through slit-like transparent regions of the mask plate, scattering the radiation and therefore adversely affecting the resolution of the optical system. As such, the photoresist regions exposed to the radiation fail to correspond to the mask plate pattern, resulting in the photoresist features being skewed. In particular, the lithography process limits the minimum achievable widths of and distances between the features of an integrated circuit. This minimum feature size dictates the density and operating speed of the integrated circuit.
Due to the high demand for densely packed integrated circuits which operate at high speeds, the semiconductor industry has developed a trimming process for reducing the lateral widths of the features of a circuit despite the limitation of lithography. FIGS. 1-3 illustrate this trimming process in detail. FIG. 1 depicts an exemplary layer, referred to in this disclosure as polysilicon layer 12, in which features are to be formed. Polysilicon layer 12 is disposed over a semiconductor substrate 10. Although not shown, a gate dielectric would likely be interposed between layer 12 and substrate 10. A photoresist layer 14 is patterned across polysilicon layer 12 via the lithography processing. Subsequently, as shown in FIG. 2, the photoresist layer 14 is subjected to an oxygen plasma to etch photoresist layer 14. As shown in FIG. 3, a photoresist layer 16 is formed which has smaller features than the original photoresist layer 14 formed by lithography (indicated by a dashed line). That is, the features of photoresist layer 16 are smaller in size than the features of photoresist layer 14. This facilitates fabricating devices with smaller critical dimensions and thus better performance. However, there is at least one problem associated with conventional trim processes: Although only lateral photoresist etch is desired, conventional trim processes also etch the photoresist features vertically. If the lateral trimming is too aggressive, a very thin photoresist may result. Consequently, during the subsequent etch of polysilicon layer 12 to define gate conductors therein, the thickness of the overlying photoresist layer 16 is insufficient to protect underlying portions of polysilicon layer 12 from being removed. As a result, the operability of the ensuing integrated circuit is compromised.
One common method employed to overcome this drawback of the trimming process has been to increase the thickness of the initial photoresist layer. However, the lithography process experiences additional problems as a result of increasing the photoresist height. For example, the imaging is blurred when the photoresist thickness exceeds the depth-of-focus of the optical system. Also the amount of ultraviolet light that scatters during penetration of the photoresist increases as the thickness of the photoresist increases, thus adversely affecting the lithography resolution. FIG. 4 depicts another problem known as tilting that can occur during the development of the photoresist. A photoresist layer 22 has been patterned upon a layer 20 disposed above a substrate 18. The photoresist features are tilted such that their vertical surfaces or sidewalls are not perpendicular to the upper surface of layer 20, thus leaving only narrow regions of layer 20 protected by the entire height of the photoresist. In addition to this problem, the photoresist could also experience resist pattern collapse in which the relatively tall features lose adhesion to the underlying layer and thus fall off.
A low initial photoresist height is therefore needed to improve lithography resolution and maintain the mechanical stability of the photoresist once it has been patterned. It would therefore be desirable to develop a method for reducing the size of photoresist features preferentially in the lateral direction, while ensuring that regions of an underlying material covered by the photoresist are protected against being etched.